1.6 KiB
This file is the authoritative current task for the main PC TX node. Read TX_NODE_STATE.md first. If chat history, this file, the shared spec, and current Git HEAD conflict, stop and report the conflict.
Current TX task
TASK = WAIT FOR RF-001A SLAVE CLKIN VERIFICATION
MASTER SERIAL = 000000000000000097c063dc323b97d3
MASTER CLKOUT COMMAND = PASS
The official source-side command completed with exit code 0:
hackrf_clock.exe -d 000000000000000097c063dc323b97d3 -o 1
The earlier hackrf_clock -r 3 output and register 29 are diagnostic information only. They do not prove whether the physical MASTER output reaches SLAVE. Do not use them as blocking criteria for common-clock verification.
The common clock remains unverified until RX laptop task VERIFY RF-001A SLAVE CLKIN reports the exact CLKIN status: clock signal detected line both before and after its finite 65536-sample RX-start. Only then may the combined result be recorded as COMMON CLOCK VERIFIED = YES.
The physical checkpoint reported by the user is: both antennas connected, both SDR USB links connected, MASTER CLKOUT connected by coaxial cable to SLAVE CLKIN, about 2 m LOS, and equal antenna polarization.
Do not repeat RF-001A transmission preparation or start RF TX in this task. Do not change PLL, sample clock, other clock outputs, registers, firmware, CPLD, Zadig or USB drivers.
TASK = WAIT FOR RF-001A SLAVE CLKIN VERIFICATION BRANCH = HEAD = MASTER SERIAL = MASTER CLKOUT COMMAND = RX COMMON CLOCK REPORT = COMMON CLOCK VERIFIED = YES / NO TX READY FOR RF-001A = YES / NO RF TX = 0 STOP.